Class QSPI
- java.lang.Object
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- org.deepjava.runtime.mpc555.driver.QSPI
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- All Implemented Interfaces:
Impc555
,IntbMpc555HB
,Ippc32
public class QSPI extends Object implements IntbMpc555HB
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Field Summary
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Fields inherited from interface org.deepjava.runtime.mpc555.Impc555
BAR, BBCMCR, BR0, BR1, BR2, BR3, CCW_A, CCW_B, CFSR0_A, CFSR0_B, CFSR1_A, CFSR1_B, CFSR2_A, CFSR2_B, CFSR3_A, CFSR3_B, CIER_A, CIER_B, CISR_A, CISR_B, CMFA_BaseAddr, CMFA_Size, CMFB_BaseAddr, CMFB_Size, CMFCTL_A, CMFCTL_B, CMFMCR_A, CMFMCR_B, CMFTST_A, CMFTST_B, CMPA, CMPB, CMPC, CMPD, CMPE, CMPF, CMPG, CMPH, COLIR, COMDRAM, COUNTA, COUNTB, CPR0_A, CPR0_B, CPR1_A, CPR1_B, DDRQA_A, DDRQA_B, DDRQS, DER, DMBR, DMOR, DPTMCR, DSCR_A, DSCR_B, DSSR_A, DSSR_B, ECR, EID, EIE, EMCR, excpCodeBase, excpCodeSize, FPECR, HSQR0_A, HSQR0_B, HSQR1_A, HSQR1_B, HSRR0_A, HSRR0_B, HSRR1_A, HSRR1_B, ICTRL, IMB, IMMR, L2U_GRA, L2U_MCR, L2U_RA0, L2U_RA1, L2U_RA2, L2U_RA3, L2U_RBA0, L2U_RBA1, L2U_RBA2, L2U_RBA3, LCTRL1, LCTRL2, LJSRR_A, LJSRR_B, LJURR_A, LJURR_B, MCPSMSCR, MDASM11AR, MDASM11BR, MDASM11SCR, MDASM11SCRD, MDASM12AR, MDASM12BR, MDASM12SCR, MDASM12SCRD, MDASM13AR, MDASM13BR, MDASM13SCR, MDASM13SCRD, MDASM14AR, MDASM14BR, MDASM14SCR, MDASM14SCRD, MDASM15AR, MDASM15BR, MDASM15SCR, MDASM15SCRD, MDASM27AR, MDASM27BR, MDASM27SCR, MDASM27SCRD, MDASM28AR, MDASM28BR, MDASM28SCR, MDASM28SCRD, MDASM29AR, MDASM29BR, MDASM29SCR, MDASM29SCRD, MDASM30AR, MDASM30BR, MDASM30SCR, MDASM30SCRD, MDASM31AR, MDASM31BR, MDASM31SCR, MDASM31SCRD, MI_GRA, MI_RA0, MI_RA1, MI_RA2, MI_RA3, MI_RBA0, MI_RBA1, MI_RBA2, MI_RBA3, MIOS1ER0, MIOS1ER1, MIOS1LVL0, MIOS1LVL1, MIOS1MCR, MIOS1RPR0, MIOS1RPR1, MIOS1SR0, MIOS1SR1, MIOS1TPCR, MIOS1VNR, MISCNT, MISRH, MISRL, MMCSM22CNT, MMCSM22ML, MMCSM22SCR, MMCSM22SCRD, MMCSM6CNT, MMCSM6ML, MMCSM6SCR, MMCSM6SCRD, MPIOSMDDR, MPIOSMDR, MPWMSM0CNTR, MPWMSM0PERR, MPWMSM0PULR, MPWMSM0SCR, MPWMSM16CNTR, MPWMSM16PERR, MPWMSM16PULR, MPWMSM16SCR, MPWMSM17CNTR, MPWMSM17PERR, MPWMSM17PULR, MPWMSM17SCR, MPWMSM18CNTR, MPWMSM18PERR, MPWMSM18PULR, MPWMSM18SCR, MPWMSM19CNTR, MPWMSM19PERR, MPWMSM19PULR, MPWMSM19SCR, MPWMSM1CNTR, MPWMSM1PERR, MPWMSM1PULR, MPWMSM1SCR, MPWMSM2CNTR, MPWMSM2PERR, MPWMSM2PULR, MPWMSM2SCR, MPWMSM3CNTR, MPWMSM3PERR, MPWMSM3PULR, MPWMSM3SCR, MSTAT, NRI, OR0, OR1, OR2, OR3, PDMCR, PISCR, PISCRIK, PITC, PITCK, PITR, PLPRCR, PLPRCRK, PORTQA_A, PORTQA_B, PORTQB_A, PORTQB_B, PORTQS, PQSPAR, PVR, QACR0_A, QACR0_B, QACR1_A, QACR1_B, QACR2_A, QACR2_B, QADC64INT_A, QADC64INT_B, QADC64MCR_A, QADC64MCR_B, QASR0_A, QASR0_B, QASR1_A, QASR1_B, QDSCI_IL, QSCI1CR, QSCI1SR, QSMCMMCR, QSPI_IL, RAMBAR, RECRAM, RJURR_A, RJURR_B, RSR, RSRK, RTC, RTCAL, RTCALK, RTCK, RTCSC, RTCSCK, RTSEC, RTSECK, SC1DR, SC1SR, SC2DR, SC2SR, SCC1R0, SCC1R1, SCC2R0, SCC2R1, SCCR, SCCRK, SCRQ, SCTQ, SGPIOCR, SGPIODT1, SGPIODT2, SIEL, SIMASK, SIPEND, SIUMCR, SIVEC, SPCR0, SPCR1, SPCR2, SPCR3, SPR1022, SPR144, SPR145, SPR146, SPR147, SPR148, SPR149, SPR150, SPR151, SPR152, SPR153, SPR154, SPR155, SPR156, SPR157, SPR158, SPR159, SPR528, SPR536, SPR560, SPR568, SPR638, SPR784, SPR785, SPR786, SPR787, SPR792, SPR793, SPR794, SPR795, SPR80, SPR81, SPR816, SPR817, SPR818, SPR819, SPR82, SPR824, SPR825, SPR826, SPR827, SPSR, SRAMA_BaseAddr, SRAMA_Size, SRAMB_BaseAddr, SRAMB_Size, SRAMMCR_A, SRAMMCR_B, stackSize, SWSR, SYPCR, sysTabBaseAddr, TBK, TBREF0, TBREF0K, TBREF1, TBREF1K, TBSCR, TBSCRK, TESR, TICR_A, TICR_B, TPUMCR_A, TPUMCR_B, TPUMCR2_A, TPUMCR2_B, TPUMCR3_A, TPUMCR3_B, TPURAM0_A, TPURAM0_B, TPURAM1_A, TPURAM1_B, TPURAM10_A, TPURAM10_B, TPURAM11_A, TPURAM11_B, TPURAM12_A, TPURAM12_B, TPURAM13_A, TPURAM13_B, TPURAM14_A, TPURAM14_B, TPURAM15_A, TPURAM15_B, TPURAM2_A, TPURAM2_B, TPURAM3_A, TPURAM3_B, TPURAM4_A, TPURAM4_B, TPURAM5_A, TPURAM5_B, TPURAM6_A, TPURAM6_B, TPURAM7_A, TPURAM7_B, TPURAM8_A, TPURAM8_B, TPURAM9_A, TPURAM9_B, TRANRAM, UIPEND, UMCR, UTSTCREG, VSRMCR
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Fields inherited from interface org.deepjava.runtime.mpc555.IntbMpc555HB
dualMappedSize, extFlashBase, extFlashSize, extRamBase, extRamSize, heapSize, SRR1init
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Fields inherited from interface org.deepjava.runtime.ppc32.Ippc32
CR, CTR, DAR, DEC, DSISR, FPR0, FPR1, FPR10, FPR11, FPR12, FPR13, FPR14, FPR15, FPR16, FPR17, FPR18, FPR19, FPR2, FPR20, FPR21, FPR22, FPR23, FPR24, FPR25, FPR26, FPR27, FPR28, FPR29, FPR3, FPR30, FPR31, FPR4, FPR5, FPR6, FPR7, FPR8, FPR9, FPSCR, LR, MSR, R0, R1, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, R2, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R3, R30, R31, R4, R5, R6, R7, R8, R9, SPR1, SPR18, SPR19, SPR22, SPR26, SPR268, SPR269, SPR27, SPR272, SPR273, SPR274, SPR275, SPR287, SPR8, SPR9, SPRG0, SPRG1, SPRG2, SPRG3, SRR0, SRR1, TBLread, TBUread, XER
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Constructor Summary
Constructors Constructor Description QSPI()
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Method Summary
All Methods Static Methods Concrete Methods Modifier and Type Method Description static void
appendTXRam(int datum)
append a value to TX Ramstatic void
appendTXRam(int[] data)
set receive Ram to datastatic void
init()
static int[]
readRxRam(int numHalfWords)
read receive ramstatic void
readRxRam(int[] buffer, int offset)
read receive ram starting at offset (in half words)static boolean
send()
initialise command ram and start spi transactionstatic void
sendBlocking()
send data in transfer ram and receive into receive ram blocks until transfer is done SPI is full duplex meaning data is transmitted and received simultaneously.
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Method Detail
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init
public static void init()
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appendTXRam
public static void appendTXRam(int[] data)
set receive Ram to data- Parameters:
data
- data as 16bit integers
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appendTXRam
public static void appendTXRam(int datum)
append a value to TX Ram- Parameters:
datum
- datam to write to TX Ram
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readRxRam
public static int[] readRxRam(int numHalfWords)
read receive ram- Parameters:
numHalfWords
- number of 16bit integers to read- Returns:
- data as 16bit integer array
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readRxRam
public static void readRxRam(int[] buffer, int offset)
read receive ram starting at offset (in half words)- Parameters:
buffer
- buffer to read into, will read buffer.length halfWordsoffset
- read offset (in half words)
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sendBlocking
public static void sendBlocking()
send data in transfer ram and receive into receive ram blocks until transfer is done SPI is full duplex meaning data is transmitted and received simultaneously.
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send
public static boolean send()
initialise command ram and start spi transaction- Returns:
- true if transaction spi done, false if busy
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