Package org.deepjava.runtime.arm32

Interface Iarm32

All Known Subinterfaces:

Icolibri_iMX6, IiMX6, IMicroZed, IZybo, Izynq7000

All Known Implementing Classes:

Blinker, Blinker, DataAbort, Decrementer, DecrementerDemo, FlinkDemo, FlinkDemo, HD44780U, IrqInterrupt, Kernel, Kernel, Kernel, MIO_DIO, MotorDemo, PrefetchAbort, Reset, Reset, RN131, RTBoard, SupervisorCall, SystemInOutReflector, SystemOutDemo, Task, TCRT1000, TCRT1000Demo, UART, UART3, UndefinedInstruction, VL53L0X, VL53L0XDemo, WatchdogDemo, WatchdogTask, WifiDemo, XADC

public interface Iarm32

Field Summary

Fields

Modifier and Type	Field	Description
static int	ACTLR
static int	CPACR
static int	CPSR
static int	D0
static int	D1
static int	D10
static int	D11
static int	D12
static int	D13
static int	D14
static int	D15
static int	D16
static int	D17
static int	D18
static int	D19
static int	D2
static int	D20
static int	D21
static int	D22
static int	D23
static int	D24
static int	D25
static int	D26
static int	D27
static int	D28
static int	D29
static int	D3
static int	D30
static int	D31
static int	D4
static int	D5
static int	D6
static int	D7
static int	D8
static int	D9
static int	FPSCR
static int	ID_ISAR0
static int	ID_ISAR1
static int	ID_ISAR2
static int	ID_ISAR3
static int	LR
static int	LR_ABT
static int	LR_FIQ
static int	LR_IRQ
static int	LR_MON
static int	LR_SVC
static int	LR_UND
static int	LR_USR
static int	MIDR
static int	MPIDR
static int	MPUIR
static int	PC
static int	R0
static int	R1
static int	R10
static int	R10_FIQ
static int	R11
static int	R11_FIQ
static int	R12
static int	R12_FIQ
static int	R2
static int	R3
static int	R4
static int	R5
static int	R6
static int	R7
static int	R8
static int	R8_FIQ
static int	R9
static int	R9_FIQ
static int	S0
static int	S1
static int	S10
static int	S11
static int	S12
static int	S13
static int	S14
static int	S15
static int	S16
static int	S17
static int	S18
static int	S19
static int	S2
static int	S20
static int	S21
static int	S22
static int	S23
static int	S24
static int	S25
static int	S26
static int	S27
static int	S28
static int	S29
static int	S3
static int	S30
static int	S31
static int	S4
static int	S5
static int	S6
static int	S7
static int	S8
static int	S9
static int	SCTLR
static int	SP
static int	SP_ABT
static int	SP_FIQ
static int	SP_IRQ
static int	SP_MON
static int	SP_SVC
static int	SP_UND
static int	SP_USR
static int	SPSR_ABT
static int	SPSR_FIQ
static int	SPSR_IRQ
static int	SPSR_MON
static int	SPSR_SVC
static int	SPSR_UND

Field Detail

R0

static final int R0

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R1

static final int R1

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R2

static final int R2

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R3

static final int R3

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R4

static final int R4

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R5

static final int R5

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R6

static final int R6

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R7

static final int R7

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R8

static final int R8

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R9

static final int R9

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R10

static final int R10

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R11

static final int R11

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R12

static final int R12

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SP

static final int SP

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LR

static final int LR

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PC

static final int PC

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SP_USR

static final int SP_USR

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LR_USR

static final int LR_USR

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CPSR

static final int CPSR

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R8_FIQ

static final int R8_FIQ

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R9_FIQ

static final int R9_FIQ

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R10_FIQ

static final int R10_FIQ

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R11_FIQ

static final int R11_FIQ

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R12_FIQ

static final int R12_FIQ

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SP_FIQ

static final int SP_FIQ

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LR_FIQ

static final int LR_FIQ

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SP_IRQ

static final int SP_IRQ

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LR_IRQ

static final int LR_IRQ

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SP_SVC

static final int SP_SVC

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LR_SVC

static final int LR_SVC

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SP_ABT

static final int SP_ABT

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LR_ABT

static final int LR_ABT

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SP_UND

static final int SP_UND

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LR_UND

static final int LR_UND

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SP_MON

static final int SP_MON

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LR_MON

static final int LR_MON

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SPSR_FIQ

static final int SPSR_FIQ

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SPSR_IRQ

static final int SPSR_IRQ

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SPSR_SVC

static final int SPSR_SVC

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SPSR_ABT

static final int SPSR_ABT

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SPSR_UND

static final int SPSR_UND

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SPSR_MON

static final int SPSR_MON

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FPSCR

static final int FPSCR

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D0

static final int D0

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D1

static final int D1

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D2

static final int D2

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D3

static final int D3

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D4

static final int D4

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D5

static final int D5

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D6

static final int D6

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D7

static final int D7

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D8

static final int D8

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D9

static final int D9

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D10

static final int D10

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D11

static final int D11

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D12

static final int D12

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D13

static final int D13

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D14

static final int D14

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D15

static final int D15

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D16

static final int D16

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D17

static final int D17

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D18

static final int D18

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D19

static final int D19

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D20

static final int D20

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D21

static final int D21

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D22

static final int D22

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D23

static final int D23

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D24

static final int D24

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D25

static final int D25

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D26

static final int D26

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D27

static final int D27

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D28

static final int D28

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D29

static final int D29

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D30

static final int D30

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D31

static final int D31

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S0

static final int S0

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S1

static final int S1

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S2

static final int S2

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S3

static final int S3

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S4

static final int S4

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S5

static final int S5

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S6

static final int S6

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S7

static final int S7

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S8

static final int S8

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S9

static final int S9

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S10

static final int S10

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S11

static final int S11

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S12

static final int S12

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S13

static final int S13

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S14

static final int S14

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S15

static final int S15

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S16

static final int S16

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S17

static final int S17

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S18

static final int S18

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S19

static final int S19

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S20

static final int S20

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S21

static final int S21

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S22

static final int S22

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S23

static final int S23

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S24

static final int S24

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S25

static final int S25

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S26

static final int S26

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S27

static final int S27

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S28

static final int S28

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S29

static final int S29

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S30

static final int S30

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S31

static final int S31

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MIDR

static final int MIDR

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MPUIR

static final int MPUIR

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MPIDR

static final int MPIDR

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ID_ISAR0

static final int ID_ISAR0

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ID_ISAR1

static final int ID_ISAR1

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ID_ISAR2

static final int ID_ISAR2

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ID_ISAR3

static final int ID_ISAR3

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SCTLR

static final int SCTLR

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ACTLR

static final int ACTLR

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CPACR

static final int CPACR

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